It is desirable to monitor the performance of digital circuits for a variety of purposes. As component and circuit physical size decrease and the complexity and speed of integrated circuits increase, entire systems comprising a plurality of functional blocks are contained in single chips. In order to monitor the performance of these systems, or portions thereof, large numbers of monitors are deployed in different locations on the chip. One method for monitoring performance of digital circuits is to count a quantity of digital activity occurring within a known period of time.
Counting digital events as a way of measuring performance has conventionally been accomplished using digital binary counter circuits. An advantage of using binary counters is the ability to count digital events precisely. In one conventional method, all digital events of interest occurring within a time period are precisely counted using a binary counter. A conventional binary counter has a bit length in the range of 10 to 20 bits with counting capacity being proportional to bit length. The capacity (i.e., bit length) of a binary counter for a particular application is designed to accommodate the quantity of expected events. The ability to conventionally count digital events for performance monitoring purposes is limited by chip space available for performance-monitoring functions, the amount of chip space necessary to construct binary counters of sufficient size, the circuit complexity needed to interconnect the performance-monitoring counters, and the operation time required to periodically interrogate each performance-monitoring counter's stored information.
Using digital counters to obtain a precise count of all digital events also has significant disadvantages. As clock speeds continue to increase, the rate and quantity of digital events occurring within the fixed time period also increase. This increase in the quantity of digital events to count quickly consumes the capacity of binary counters. Increasing counter capacity often slows overall system operation time due to the long serial scan vectors necessary to interrogate large counters for data retrieval. The complexity of large binary counters, and the accompanying circuitry necessary to interconnect large digital counters to other performance monitoring logic, also increases costs and occupies valuable integrated circuit space.
In many digital event performance evaluation applications, a precise digital event count, is not necessary. In some evaluation applications, an approximate count of the entire population is adequate, for example, in regulating system chip power or dispatching chip cooling mechanisms. One method for obtaining an approximate count of a population of events is through statistical analysis of samples taken from the population, from which inferences regarding the balance of the population are made.
A method and circuit for monitoring the performance of digital systems that address the aforementioned problems, as well as other related problems, are therefore desirable.